Invention Grant
- Patent Title: Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
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Application No.: US14694540Application Date: 2015-04-23
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Publication No.: US09786633B2Publication Date: 2017-10-10
- Inventor: Rabindra N. Das , Peter G. Murphy , Karen E. Magoon , Noyan Kinayman , Michael J. Barbieri , Timothy M. Hancock , Mark A. Gouker
- Applicant: Massachusetts Institute of Technology
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institute of Technology
- Current Assignee: Massachusetts Institute of Technology
- Current Assignee Address: US MA Cambridge
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00

Abstract:
A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.
Public/Granted literature
- US20170098627A1 INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES Public/Granted day:2017-04-06
Information query
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