Invention Grant
- Patent Title: Semiconductor device comprising oxide semiconductor layer including regions with different concentrations of resistance-reducing elements
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Application No.: US13832654Application Date: 2013-03-15
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Publication No.: US09786793B2Publication Date: 2017-10-10
- Inventor: Sachiaki Tezuka
- Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., LTD.
- Current Assignee: Semiconductor Energy Laboratory Co., LTD.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Nixon Peabody LLP
- Agent Jeffrey L. Costellia
- Priority: JP2012-075612 20120329; JP2012-090711 20120412
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/16 ; H01L21/00 ; H01L29/24 ; H01L21/47 ; H01L29/786

Abstract:
To increase the on-state current of a transistor whose channel is formed in an oxide semiconductor layer. To provide a transistor where a resistance-reducing element is introduced into a region of an oxide semiconductor layer which overlaps with part of a source or drain or part of a gate. For example, the thickness of a region of a conductive layer serving as a source or drain or a gate (at least part of a region overlapping with an oxide semiconductor layer) is made smaller than that of the other region of the conductive layer. A resistance-reducing element is introduced into the oxide semiconductor layer through the conductive layer thinned partly, thereby obtaining the oxide semiconductor layer where the resistance-reducing element is introduced into the region overlapping with part of the source or drain or part of the gate. Thus, the on-state current of the transistor can be increased.
Public/Granted literature
- US20130256656A1 TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2013-10-03
Information query
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