A device implementing a forward error correction data transmission system may include at least one processor circuit. The at least one processor circuit may be configured to perform line encoding on a data stream received from a media access control (MAC) module, and periodically insert alignment markers after every number of blocks of the data stream, where the alignment markers are determined based at least in part on a data rate of an associated port. The at least one processor circuit may be further configured to transcode the data stream, where each alignment marker remains contiguous in the transcoded data stream. The at least one processor circuit may be further configured to add parity information to the transcoded data stream. The at least one processor circuit may be further configured to transmit the transcoded data stream over at least one physical lane of the associated port.