Invention Grant
- Patent Title: Method and apparatus for compensating for sampling clock-offset
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Application No.: US15172487Application Date: 2016-06-03
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Publication No.: US09787464B2Publication Date: 2017-10-10
- Inventor: Sujit Jos , Kiran Bynam , Ashutosh Deepak Gore , Chandrashekhar Thejaswi Ps , Chang Soon Park , Young Jun Hong , Manoj Choudhary
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: NSIP Law
- Priority: IN2790/CHE/2015 20150603; KR10-2016-0015236 20160205
- Main IPC: H04L7/02
- IPC: H04L7/02 ; H04W56/00
Abstract:
A method for compensating for a sampling clock-offset includes calculating a positive threshold and a negative threshold of pulse-shaped data symbols to be received, calculating a positive sum ratio and a negative sum ratio from received samples, and compensating for a sampling clock-offset in response to the positive sum ratio being less than or equal to the positive threshold and the negative sum ratio being less than or equal to the negative threshold.
Public/Granted literature
- US20160359613A1 METHOD AND APPARATUS FOR COMPENSATING FOR SAMPLING CLOCK-OFFSET Public/Granted day:2016-12-08
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