Invention Grant
- Patent Title: High order hybrid phase locked loop with digital scheme for jitter suppression
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Application No.: US15064975Application Date: 2016-03-09
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Publication No.: US09787466B2Publication Date: 2017-10-10
- Inventor: Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi
- Applicant: Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi
- Applicant Address: US MD Hanover
- Assignee: Ciena Corporation
- Current Assignee: Ciena Corporation
- Current Assignee Address: US MD Hanover
- Agency: Osha Liang LLP
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H04L7/033 ; H03L7/099 ; H03L7/085 ; H03L7/08 ; H03L7/23 ; H03L7/07 ; H03L7/06 ; H03L7/193 ; H03L7/18 ; H03L7/197 ; H03L7/093

Abstract:
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.
Public/Granted literature
- US20170264425A1 HIGH ORDER HYBRID PHASE LOCKED LOOP WITH DIGITAL SCHEME FOR JITTER SUPPRESSION Public/Granted day:2017-09-14
Information query
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