According to one embodiment, there is provided an image data receiving device including 1st to Kth lane reproduction circuits, 1st to Kth timing adjustment circuits, 1st to Kth lane reproduction outputs, and 1st to (K−1)th selectors. The Nth lane reproduction circuit transmits data of an nth pixel. The (N+1)th lane reproduction circuit transmits data of an (n+1)th pixel adjacent to the nth pixel. The Nth timing adjustment circuit has an input terminal electrically connected to the Nth lane reproduction circuit. The (N+1)th timing adjustment circuit has an input terminal electrically connected to the (N+1)th lane reproduction circuit. The Nth lane reproduction output can be electrically connected to an output terminal of the Nth timing adjustment circuit. The Nth selector can electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output.