Invention Grant
- Patent Title: Layout and timing schemes for ping-pong readout architecture
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Application No.: US14989067Application Date: 2016-01-06
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Publication No.: US09787928B2Publication Date: 2017-10-10
- Inventor: Dexue Zhang , Yingying Wang , Loc Truong , Steven Huang
- Applicant: Forza Silicon Corporation
- Applicant Address: US CA Pasadena
- Assignee: Forza Silicon Corporation
- Current Assignee: Forza Silicon Corporation
- Current Assignee Address: US CA Pasadena
- Agency: Mountain IP, PLLC
- Main IPC: H04N5/378
- IPC: H04N5/378 ; H04N5/357 ; H04N5/374 ; H01L27/146
Abstract:
Ping-pong readout architecture allows for faster frame rates in CMOS image sensors. However, various problems are created by this architecture due to cross-talk between components. Provided herein are novel ping-pong readout layouts which better isolate components to reduce crosstalk issues. Also provided herein are novel timing schemes for operating ping-pong readout circuits which prevent crosstalk signal spikes or readout corruption.
Public/Granted literature
- US20160198114A1 Layout and Timing Schemes for Ping-Pong Readout Architecture Public/Granted day:2016-07-07
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