Invention Grant
- Patent Title: Electronic package that includes finned vias
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Application No.: US14969514Application Date: 2015-12-15
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Publication No.: US09795026B2Publication Date: 2017-10-17
- Inventor: Nayandeep K. Mahanta , Joshua D. Heppner , Adel A. Elsherbini
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/18 ; H05K1/11

Abstract:
The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.
Public/Granted literature
- US20170171957A1 ELECTRONIC PACKAGE THAT INCLUDES FINNED VIAS Public/Granted day:2017-06-15
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