- Patent Title: Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
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Application No.: US14096514Application Date: 2013-12-04
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Publication No.: US09795033B2Publication Date: 2017-10-17
- Inventor: Shingo Yoshioka , Hiroaki Fujiwara
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: PANASONIC CORPORATION
- Current Assignee: PANASONIC CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2009-015052 20090127; JP2009-253131 20091104
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H05K1/11 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; G11B5/48 ; H05K1/18 ; H05K3/18 ; H01L21/66 ; H01L23/31 ; H01L21/56
Abstract:
A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
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