Invention Grant
- Patent Title: Memory having a plurality of memory cells and a plurality of word lines
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Application No.: US14502077Application Date: 2014-09-30
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Publication No.: US09799412B2Publication Date: 2017-10-24
- Inventor: Makoto Kitagawa , Yogesh Luthra
- Applicant: Sony Semiconductor Solutions Corporation
- Applicant Address: JP Kanagawa
- Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sheridan Ross P.C.
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C29/00 ; G11C13/00
Abstract:
A memory includes a plurality of replacement word lines interspersed among the plurality of word lines. The memory also includes a word line control circuit configured to apply different voltages to different word lines of the plurality of word lines based on positions of the word lines, and to replace a defective word line of the plurality of word lines with a replacement word line.
Public/Granted literature
- US20160093402A1 MEMORY WITH DISTRIBUTED REPLACEMENT WORD LINES Public/Granted day:2016-03-31
Information query
