Invention Grant
- Patent Title: Bump structure design for stress reduction
-
Application No.: US15488972Application Date: 2017-04-17
-
Publication No.: US09799582B2Publication Date: 2017-10-24
- Inventor: Hsien-Wei Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/29 ; H01L23/00

Abstract:
Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.
Public/Granted literature
- US20170221789A1 BUMP STRUCTURE DESIGN FOR STRESS REDUCTION Public/Granted day:2017-08-03
Information query
IPC分类: