Invention Grant
- Patent Title: Method of forming inner spacers on a nano-sheet/wire device
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Application No.: US15398335Application Date: 2017-01-04
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Publication No.: US09799748B1Publication Date: 2017-10-24
- Inventor: Ruilong Xie , Min Gyu Sung , Chanro Park , Hoon Kim
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/66 ; H01L21/306 ; H01L21/308

Abstract:
A method includes forming a stack of semiconductor material layers above a substrate. The stack includes at least one first semiconductor material layer and at least one second semiconductor material layer. A first etching process is performed on the stack to define cavities. The cavities expose end portions of the first and second semiconductor material layers. Portions of the first semiconductor material layer are removed to define end recesses. A layer of insulating material is formed in the end recesses and at least partially fills the cavities. A second etching process is performed on the stack to remove end portions of the at least one second semiconductor material layer and to remove portions of the layer of insulating material in the cavities not disposed between the first and second semiconductor material layers so as to form inner spacers on ends of the at least one first semiconductor material layer.
Information query
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