Invention Grant
- Patent Title: Method and circuit for testing successive approximation ADC
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Application No.: US15332630Application Date: 2016-10-24
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Publication No.: US09800255B2Publication Date: 2017-10-24
- Inventor: Shih-Hsiung Huang
- Applicant: REALTEK SEMICONDUCTOR CORPORATION
- Applicant Address: TW Hsinchu
- Assignee: REALTEK SEMICONDUCTOR CORPORATION
- Current Assignee: REALTEK SEMICONDUCTOR CORPORATION
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C., Intellectual Property Attorneys
- Agent Anthony King
- Priority: TW104137108A 20151111
- Main IPC: H03M1/10
- IPC: H03M1/10 ; H03M1/46

Abstract:
This invention discloses a method and a circuit for testing a successive approximation ADC. The test method includes the following steps: receiving a plurality of digital output codes of a SAR ADC; counting the number of odd numbers and the number of even numbers of the digital output codes; and determining whether an error occurs in the SAR ADC based on the number of odd numbers and the number of even numbers.
Public/Granted literature
- US20170134036A1 Method and Circuit for Testing Successive Approximation ADC Public/Granted day:2017-05-11
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