Invention Grant
- Patent Title: Semiconductor device manufacturing method
-
Application No.: US15368640Application Date: 2016-12-04
-
Publication No.: US09806007B2Publication Date: 2017-10-31
- Inventor: Katsuhito Kamachi , Hideaki Tamimoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2016-016104 20160129
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/495 ; H01L21/48 ; H01L23/00

Abstract:
A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.
Public/Granted literature
- US20170221803A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2017-08-03
Information query
IPC分类: