Invention Grant
- Patent Title: Prototyping of electronic circuits with edge interconnects
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Application No.: US15295385Application Date: 2016-10-17
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Publication No.: US09806030B2Publication Date: 2017-10-31
- Inventor: Jason M. Kulick , Tian Lu
- Applicant: Indiana Integrated Circuits, LLC
- Applicant Address: US IN South Bend
- Assignee: Indiana Integrated Circuits, LLC
- Current Assignee: Indiana Integrated Circuits, LLC
- Current Assignee Address: US IN South Bend
- Agency: The Webb Law Firm
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/538 ; H01L21/48 ; H01L21/52

Abstract:
In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities are formed in the substrate, a conductive pad is formed in each cavity, and one or more conductive traces are formed on the substrate. Each conductive trace connects a conductive pad to a location, node, or terminal of the electrical circuit. A part of the substrate is removed to form the assembly that includes the electrical circuit, the one or more conductive traces, and a portion of each conductive pad projecting or protruding from the substrate. The electrical circuit can be formed on the substrate, which can be a PCB, or can be formed on a microchip supported by the substrate, which can be formed of semiconductor material, e.g., a semiconductor wafer.
Public/Granted literature
- US20170125350A1 Prototyping of Electronic Circuits with Edge Interconnects Public/Granted day:2017-05-04
Information query
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