Invention Grant
- Patent Title: Chip-on-wafer package and method of forming same
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Application No.: US15141589Application Date: 2016-04-28
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Publication No.: US09806055B2Publication Date: 2017-10-31
- Inventor: Chen-Hua Yu , Ming-Fa Chen , Sung-Feng Yeh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L21/56 ; H01L21/768 ; H01L23/31 ; H01L23/538 ; H01L25/065 ; H01L25/00 ; H01L23/532 ; H01L21/48 ; H01L23/498

Abstract:
A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.
Public/Granted literature
- US20160247779A1 CHIP-ON-WAFER PACKAGE AND METHOD OF FORMING SAME Public/Granted day:2016-08-25
Information query
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