Invention Grant
- Patent Title: Semiconductor device and method of manufacturing the semiconductor device
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Application No.: US14748909Application Date: 2015-06-24
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Publication No.: US09806149B2Publication Date: 2017-10-31
- Inventor: Masahiro Tomioka
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2014-130823 20140625
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/06 ; H01L29/66 ; H01L29/78

Abstract:
A MISFET has a threshold voltage that is not undesirably increased due to channel narrowing of the MISFET, and the MISFET is reduced in size and increased in withstand voltage. An anti-inversion p-type channel stopper region provided below an element isolation trench has an end that projects toward a channel region below a gate oxide film, and terminates short of the channel region. That is, the end is offset from the end of the channel region (the end of the element isolation trench). This suppresses diffusion in a lateral direction (channel region direction) of an impurity in the p-type channel stopper region, and thus suppresses a decrease in carrier concentration at the end of the channel region. As a result, a local increase in threshold voltage is suppressed.
Public/Granted literature
- US20150380490A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE Public/Granted day:2015-12-31
Information query
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