A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.