Invention Grant
- Patent Title: Semiconductor arrangement and formation thereof
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Application No.: US15589027Application Date: 2017-05-08
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Publication No.: US09812416B2Publication Date: 2017-11-07
- Inventor: Jiun Yi Wu , Hsueh-Lung Cheng , Shou-Yi Wang
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsin-Chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L23/00 ; H01L23/522 ; H01L21/66 ; H01L21/768

Abstract:
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.
Public/Granted literature
- US20170243842A1 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF Public/Granted day:2017-08-24
Information query
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