Invention Grant
- Patent Title: Biased ESD circuit
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Application No.: US14834554Application Date: 2015-08-25
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Publication No.: US09812440B2Publication Date: 2017-11-07
- Inventor: Kenneth P. Snowdon , Taeghyun Kang , Yongliang Li
- Applicant: Fairchild Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H02H9/04
- IPC: H02H9/04 ; H01L27/02

Abstract:
This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
Public/Granted literature
- US20160064374A1 BIASED ESD CIRCUIT Public/Granted day:2016-03-03
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