Invention Grant
- Patent Title: Method for manufacturing a semiconductor device with increased breakdown voltage
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Application No.: US15000786Application Date: 2016-01-19
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Publication No.: US09812554B2Publication Date: 2017-11-07
- Inventor: Tomoyuki Sakuma , Shinya Sato , Noboru Yokoyama , Akihiro Shimada
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: JP2015-173209 20150902
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L21/266 ; H01L21/3065 ; H01L29/423

Abstract:
According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.
Public/Granted literature
- US20170062585A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2017-03-02
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