A display apparatus according to the present invention includes: N driver ICs (first to third driver ICs); N or more bidirectional memories (first to third bidirectional memories) that simultaneously allow data writing and data reading; a phase locked loop that converts an input clock to an output clock; a write controller that writes data to the plurality of bidirectional memories in synchronization with the input clock; and a read controller that reads the data from the plurality of bidirectional memories and causes the data to be output to the plurality of driver ICs in synchronization with the output clock. A frequency of the output clock is smaller than a frequency of the input clock and is larger than 1/N times the frequency of the input clock.