A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N−1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.