Invention Grant
- Patent Title: Method for manufacturing a device isolation structure
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Application No.: US15438204Application Date: 2017-02-21
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Publication No.: US09824914B2Publication Date: 2017-11-21
- Inventor: Guangli Yang , Xianyong Pu , Li Liu , Chihchung Tai , Gangning Wang , Hong Sun
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN201410548682 20141016
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/762 ; H01L21/763 ; H01L23/552 ; H01L21/765

Abstract:
A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, and each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.
Public/Granted literature
- US20170162433A1 METHOD FOR MANUFACTURING A DEVICE ISOLATION STRUCTURE Public/Granted day:2017-06-08
Information query
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