Invention Grant
- Patent Title: Semiconductor arrangement with capacitor and method of fabricating the same
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Application No.: US14144676Application Date: 2013-12-31
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Publication No.: US09825040B2Publication Date: 2017-11-21
- Inventor: Chern-Yow Hsu , Ming Chyi Liu , Shih-Chang Liu , Chia-Shiung Tsai , Xiaomeng Chen , Chen-Jong Wang
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsin-Chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L49/02
Abstract:
A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
Public/Granted literature
- US20150187777A1 SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR AND METHOD OF FABRICATING THE SAME Public/Granted day:2015-07-02
Information query
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