Invention Grant
- Patent Title: Wiring structure for solid-state imaging device
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Application No.: US14553586Application Date: 2014-11-25
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Publication No.: US09825072B2Publication Date: 2017-11-21
- Inventor: Hirohisa Ohtsuki
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2012-144748 20120627
- Main IPC: H01L27/00
- IPC: H01L27/00 ; H01L27/146 ; H04N5/3745

Abstract:
A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.
Public/Granted literature
- US20150076326A1 SOLID-STATE IMAGING DEVICE Public/Granted day:2015-03-19
Information query
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