Invention Grant
- Patent Title: Dummy bit line MOS capacitor and device using the same
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Application No.: US14961815Application Date: 2015-12-07
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Publication No.: US09825146B2Publication Date: 2017-11-21
- Inventor: Jeong Sub Lim
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon
- Assignee: SK HYNIX INC.
- Current Assignee: SK HYNIX INC.
- Current Assignee Address: KR Icheon
- Priority: KR10-2012-0077878 20120717
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/94 ; H01L27/02 ; G11C7/18 ; H01L21/768 ; H01L21/02 ; H01L21/265 ; H01L27/108

Abstract:
A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.
Public/Granted literature
- US20160087072A1 DUMMY BIT LINE MOS CAPACITOR AND DEVICE USING THE SAME Public/Granted day:2016-03-24
Information query
IPC分类: