Invention Grant
- Patent Title: Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device
-
Application No.: US13503861Application Date: 2009-11-19
-
Publication No.: US09825162B2Publication Date: 2017-11-21
- Inventor: Philippe Renaud , Bruce Green
- Applicant: Philippe Renaud , Bruce Green
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Agent Bruce M. Green
- International Application: PCT/IB2009/056014 WO 20091119
- International Announcement: WO2011/061573 WO 20110526
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L21/8252 ; H01L27/06 ; H01L29/66 ; H01L29/20 ; H01L29/417
Abstract:
A vertical power transistor device comprises: a substrate formed from a III-V semiconductor material and a multi-layer stack at least partially accommodated in the substrate. The multi-layer stack comprises: a semi-insulating layer disposed adjacent the substrate and a first layer formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer. The multi-layer stack also comprises a second layer formed from a second III-V semiconductor material disposed adjacent the first layer and a heterojunction is formed at an interface of the first and second layers.
Public/Granted literature
Information query
IPC分类:
