Invention Grant
- Patent Title: Partial, self-biased isolation in semiconductor devices
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Application No.: US14971896Application Date: 2015-12-16
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Publication No.: US09825169B2Publication Date: 2017-11-21
- Inventor: Xin Lin , Xu Cheng , Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/08 ; H01L21/761 ; H01L21/265 ; H01L29/66
Abstract:
A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the drain region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the drain region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the drain region.
Public/Granted literature
- US20170179279A1 PARTIAL, SELF-BIASED ISOLATION IN SEMICONDUCTOR DEVICES Public/Granted day:2017-06-22
Information query
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