A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.