A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines.