Invention Grant
- Patent Title: Multi-level flash storage device with minimal read latency
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Application No.: US14839535Application Date: 2015-08-28
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Publication No.: US09837145B2Publication Date: 2017-12-05
- Inventor: Bruce Alexander Wilson
- Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Current Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Sheridan Ross P.C.
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C11/56 ; G11C16/26

Abstract:
A memory system, non-volatile solid-state memory, and a method of efficiently reading data from a flash memory array are disclosed. The disclosed memory system includes a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being configured to store at least two bits per cell and being organized into pages, and a controller configured to read any bit of data from a page of the flash memory array by applying a single threshold voltage to the flash memory array. Reading data from the flash memory array with a single threshold greatly decreases the latency associated with the read operation.
Public/Granted literature
- US20170062045A1 MULTI-LEVEL FLASH STORAGE DEVICE WITH MINIMAL READ LATENCY Public/Granted day:2017-03-02
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