Invention Grant
- Patent Title: Methods of forming patterns of a semiconductor devices
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Application No.: US15223710Application Date: 2016-07-29
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Publication No.: US09837273B2Publication Date: 2017-12-05
- Inventor: Jong-Sub Lee , Kyoung-Ha Eom , Ha-Neul Lee , Sang-Gyo Chung
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2015-0141499 20151008
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/311 ; H01L21/3213 ; H01L27/108

Abstract:
A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.
Public/Granted literature
- US20170103891A1 METHODS OF FORMING PATTERNS OF A SEMICONDUCTOR DEVICES Public/Granted day:2017-04-13
Information query
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