- Patent Title: Wafer level chip scale package and method of manufacturing the same
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Application No.: US14192374Application Date: 2014-02-27
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Publication No.: US09837278B2Publication Date: 2017-12-05
- Inventor: Yu-Hsiang Hu , Wei-Yu Chen , Hung-Jui Kuo , Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King; Kay Yang
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/304 ; H01L25/07 ; H01L23/31 ; H01L23/14 ; H01L23/15 ; H01L25/065 ; H01L23/00 ; H01L21/56
Abstract:
A semiconductor structure includes a die including a top surface and a sidewall, and a molding surrounding the die and including a top surface, a sidewall interfacing with the sidewall of the die, and a curved surface including a curvature greater than zero and coupling the sidewall of the molding with the top surface of the molding.
Public/Granted literature
- US20150243573A1 WAFER LEVEL CHIP SCALE PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2015-08-27
Information query
IPC分类:
