Invention Grant
- Patent Title: Methods of forming 3-D circuits with integrated passive devices
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Application No.: US15607888Application Date: 2017-05-30
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Publication No.: US09837299B2Publication Date: 2017-12-05
- Inventor: Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: INVENSAS CORPORATION
- Current Assignee: INVENSAS CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/683
- IPC: H01L21/683 ; H01L21/768 ; H01L23/367 ; H01L23/48 ; H01L23/538 ; H01L23/58 ; H01L23/00 ; H01L25/065 ; H01L25/16 ; H01L25/00 ; H01L27/02 ; H01L27/06
Abstract:
Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.
Public/Granted literature
- US20170301577A1 METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES Public/Granted day:2017-10-19
Information query
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