Invention Grant
- Patent Title: Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
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Application No.: US13917982Application Date: 2013-06-14
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Publication No.: US09837303B2Publication Date: 2017-12-05
- Inventor: Yaojian Lin , Kang Chen , Yu Gu , Pandi Chelvam Marimuthu
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associate, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48 ; H01L23/00 ; H01L23/31 ; H01L23/538 ; H01L21/56 ; H01L23/498

Abstract:
A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
Public/Granted literature
- US20130277851A1 Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units Public/Granted day:2013-10-24
Information query
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