Invention Grant
- Patent Title: Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief
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Application No.: US14257850Application Date: 2014-04-21
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Publication No.: US09837336B2Publication Date: 2017-12-05
- Inventor: Won Kyoung Choi , Chang Bum Yong , Jae Hun Ku
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Pte. Ltd.
- Current Assignee: STATS ChipPAC, Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/31 ; H01L21/683 ; H01L25/065 ; H01L21/768 ; H01L23/00

Abstract:
A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.
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Information query
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