Invention Grant
- Patent Title: Enhanced board level reliability for wafer level packages
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Application No.: US14496049Application Date: 2014-09-25
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Publication No.: US09837368B2Publication Date: 2017-12-05
- Inventor: Peter R. Harper , Martin Mason , Arkadii V. Samoilov
- Applicant: Maxim Integrated Products, Inc.
- Applicant Address: US CA San Jose
- Assignee: Maxim Integrated Products, Inc.
- Current Assignee: Maxim Integrated Products, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Advent, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L21/56

Abstract:
A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.
Public/Granted literature
- US20150255413A1 ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES Public/Granted day:2015-09-10
Information query
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