Invention Grant
- Patent Title: Fan-out 3D IC integration structure without substrate and method of making the same
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Application No.: US14954679Application Date: 2015-11-30
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Publication No.: US09837378B2Publication Date: 2017-12-05
- Inventor: Rezaur Rahman Khan , Sam Ziqun Zhao
- Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/31 ; H01L23/48 ; H01L23/50 ; H01L23/528 ; H01L23/00

Abstract:
A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.
Public/Granted literature
- US20170117251A1 Fan-out 3D IC Integration Structure without Substrate and Method of Making the Same Public/Granted day:2017-04-27
Information query
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