Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US15089630Application Date: 2016-04-04
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Publication No.: US09837382B2Publication Date: 2017-12-05
- Inventor: Shinji Watanabe , Toshihiro Iwasaki , Michiaki Tamakawa
- Applicant: J-DEVICES CORPORATION
- Applicant Address: JP Oita
- Assignee: J-DEVICE CORPORATION
- Current Assignee: J-DEVICE CORPORATION
- Current Assignee Address: JP Oita
- Agency: Typha IP LLC
- Priority: JP2015-080718 20150410
- Main IPC: H01L23/373
- IPC: H01L23/373 ; H01L25/065 ; H01L25/00 ; H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L21/60 ; H01L23/31 ; H01L23/36 ; H01L23/498

Abstract:
Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.
Public/Granted literature
- US20160300779A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-10-13
Information query
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