Invention Grant
- Patent Title: Semiconductor device with anti-fuse memory element
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Application No.: US14874405Application Date: 2015-10-03
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Publication No.: US09837424B2Publication Date: 2017-12-05
- Inventor: Yoshiki Yamamoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2014-204596 20141003
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/112 ; H01L23/525

Abstract:
An insulating film, which is sandwiched between a gate electrode formed on an SOI layer constituting an SOI substrate and an epitaxial layer formed on the SOI layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element.
Public/Granted literature
- US20160099251A1 SEMICONDUCTOR DEVICE Public/Granted day:2016-04-07
Information query
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