Invention Grant
- Patent Title: Solder void reduction between electronic packages and printed circuit boards
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Application No.: US15220771Application Date: 2016-07-27
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Publication No.: US09839128B2Publication Date: 2017-12-05
- Inventor: Phillip D. Isaacs
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: DeLizio Law, PLLC
- Main IPC: H05K7/10
- IPC: H05K7/10 ; H05K7/12 ; H05K1/18 ; H05K3/42 ; H05K1/02 ; H05K1/11 ; H05K3/34

Abstract:
An apparatus includes a printed circuit board. The printed circuit board includes at least one conductive layer on top a first dielectric layer, wherein the at least one conductive layer comprises at least one of a ground plane and a power plane. The printed circuit board includes a second dielectric layer on top of the at least one conductive layer. The printed circuit board includes a thermal pad on top of the second dielectric layer. The printed circuit board is fabricated by forming at least one plated through hole for electrically coupling the thermal pad to the at least one conductive layer. The printed circuit board is fabricated by backdrilling the at least one plated through hole to remove a portion of the conductive material, wherein subsequent to the backdrilling the conductive material remaining in the at least one plated through hole electrically couples one or more of the at least one conductive layer to the thermal pad.
Public/Granted literature
- US20160338200A1 SOLDER VOID REDUCTION BETWEEN ELECTRONIC PACKAGES AND PRINTED CIRCUIT BOARDS Public/Granted day:2016-11-17
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