A demultiplexer circuit (12) of a display device according to one aspect of the present invention includes signal input lines (Vn), control lines (BSW, GSW, and RSW), and sampling transistors (13R2, 13G2, and 13B1). Sampling transistors connected to one signal input line includes first and second sampling transistors. A first sampling transistor (13B1) includes a control electrode (17) which branches to a first branch part (17a) and a second branch part (17b), either one of an input electrode (15) and an output electrode (18) that are disposed between a first branch part (17a) and a second branch part (17b), and other one of an input electrode (15) and an output electrode (18) that are disposed outside of a first branch part (17a) and a second branch part (17b).