Invention Grant
- Patent Title: Forming interconnect structures utilizing subtractive paterning techniques
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Application No.: US15082844Application Date: 2016-03-28
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Publication No.: US09842800B2Publication Date: 2017-12-12
- Inventor: Robert A. May
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48

Abstract:
Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate core, and forming at least one conductive interconnect structure disposed on the substrate core. The conductive interconnect structure may comprise a first side that is directly disposed on a surface of the substrate core, and a second side opposite the first side, wherein the second side comprises a greater length than a length of the first side.
Public/Granted literature
- US20170278780A1 FORMING INTERCONNECT STRUCTURES UTILIZING SUBTRACTIVE PATERNING TECHNIQUES Public/Granted day:2017-09-28
Information query
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