An apparatus and method for Fast Fourier Transform (FFT) address generation is disclosed. The apparatus may include a counter circuit and circuitry configured to load an initial value into a counter circuit. The circuitry may be further configured to generate first and second output values by formatting a current value of the counter, and increment the current value of the counter circuit by an increment value to generate a next value. The circuitry may also be configured to modify the increment value in response to a determination that the next value is equal to a target value.