Invention Grant
- Patent Title: Automatic architecture placement guidance
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Application No.: US14937547Application Date: 2015-11-10
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Publication No.: US09852254B2Publication Date: 2017-12-26
- Inventor: Jiri George Janac
- Applicant: Arteris, Inc.
- Applicant Address: US CA Campbell
- Assignee: ARTERIS, Inc.
- Current Assignee: ARTERIS, Inc.
- Current Assignee Address: US CA Campbell
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
On-chip data transport network architectural units are assigned preferred placement locations based on architecture-level constraints. The preferred placement locations are used to generate placement constraints for a place and route tool. The placement constraints are applied to cells that are synthesized from each architectural unit. Constraints are blockages, fences, regions, and guides. Preferred placement locations are mapped to grid elements. Each grid elements defines a cell placement constraint.
Public/Granted literature
- US20170132350A1 AUTOMATIC ARCHITECTURE PLACEMENT GUIDANCE Public/Granted day:2017-05-11
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