Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits

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US09852258B1 Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits 有权

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Patent Title: Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits
Application No.: US14675551

Application Date: 2015-03-31
Publication No.: US09852258B1

Publication Date: 2017-12-26
Inventor: Paul C. Foster , Walter E. Hartong , Jinduo Sun
Applicant: Cadence Design Systems, Inc.
Applicant Address: US CA San Jose
Assignee: Cadence Design Systems, Inc.
Current Assignee: Cadence Design Systems, Inc.
Current Assignee Address: US CA San Jose
Agency: Vista IP Law Group, LLP
Main IPC: G06F17/50
IPC: G06F17/50

Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits

Abstract:

Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.

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