Invention Grant
- Patent Title: Memory testing circuit and testing method using same
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Application No.: US14978885Application Date: 2015-12-22
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Publication No.: US09852808B2Publication Date: 2017-12-26
- Inventor: Liang Qian
- Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
- Applicant Address: CN Shanghai
- Assignee: Shanghai Huanhong Grace Semiconductor Manufacturing Corporation
- Current Assignee: Shanghai Huanhong Grace Semiconductor Manufacturing Corporation
- Current Assignee Address: CN Shanghai
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: CN201510052256 20150131
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/38 ; G11C29/12 ; G11C29/36 ; G11C29/48 ; G11C16/00

Abstract:
A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.
Public/Granted literature
- US20160225465A1 MEMORY TESTING CIRCUIT AND TESTING METHOD USING SAME Public/Granted day:2016-08-04
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