Invention Grant
- Patent Title: Chip fuse and manufacturing method therefor
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Application No.: US14432128Application Date: 2012-09-28
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Publication No.: US09852868B2Publication Date: 2017-12-26
- Inventor: Katsuya Yamagishi , Hideki Seino
- Applicant: KAMAYA ELECTRIC CO., LTD.
- Applicant Address: JP Ayase-shi
- Assignee: KAMAYA ELECTRIC CO., LTD.
- Current Assignee: KAMAYA ELECTRIC CO., LTD.
- Current Assignee Address: JP Ayase-shi
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- International Application: PCT/JP2012/075009 WO 20120928
- International Announcement: WO2014/049809 WO 20140403
- Main IPC: G06F1/16
- IPC: G06F1/16 ; H05K5/00 ; H05K7/00 ; H01H85/00 ; H01H85/046 ; H01H69/02 ; H01H85/48 ; H01H85/38 ; H01H85/143

Abstract:
In a chip fuse, a heat-storing layer is formed on an insulated substrate, a fuse film is formed on the heat-storing layer, and a protective film is formed on the fuse element section. The chip fuse includes surface electrode sections on both ends in the length direction of the chip fuse and a fuse element section between the surface electrode sections. In this chip fuse, a rectangular bank section is formed over the heat-storing layer and the surface electrode sections to surround the fuse element section, and a first protective layer is formed on the inner side of the bank section. In addition, during the bank formation process, a sheet-like photosensitive-group-containing material is laminated on the fuse element section, surface electrode sections, and heat-storing layer, and the sheet-like photosensitive-group-containing material is exposed to ultraviolet light and developed to form the rectangular bank section.
Public/Granted literature
- US20150270085A1 CHIP FUSE AND MANUFACTURING METHOD THEREFOR Public/Granted day:2015-09-24
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