Invention Grant
- Patent Title: Interposer, semiconductor package structure, and semiconductor process
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Application No.: US15178066Application Date: 2016-06-09
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Publication No.: US09852971B1Publication Date: 2017-12-26
- Inventor: Wen-Long Lu , Min Lung Huang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/31 ; H01L21/48

Abstract:
An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via and an isolation material. The metal layer defines at least one through hole having a side wall. The at least one metal via is disposed in the through hole. A space is defined between the at least one metal via and the side wall of the through hole, and the isolation material fills the space. The redistribution layer is disposed on a surface of the interconnection structure and is electrically connected to the metal via.
Public/Granted literature
- US20170358527A1 INTERPOSER, SEMICONDUCTOR PACKAGE STRUCTURE, AND SEMICONDUCTOR PROCESS Public/Granted day:2017-12-14
Information query
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